1. Field of the Invention
This invention relates to high speed random access memories and particularly to a system where the bit line output stage uses on-chip logic.
2. Description of the Prior Art
Various techniques have been proposed in the prior art to utilize memories with less than so-called "all good" memory elements. Auxiliary or redundant elements have been proposed to replace unusable ones once the bad element has been identified. The production of large storage devices having a large number of storage elements will not produce acceptable yields if it is necessary to exclude from use arrays having unusable individual storage elements. Accordingly, to achieve economic production less than perfect memories are deemed acceptable and the faulty storage element has either been replaced or eliminated so that the matrix itself may be operable despite the presence of individually defective storage elements.
Hence, the internal source of bit errors, defective individual elements, may be corrected by using redundant elements. This technique is distinguishable from approaches where the external symptoms of a memory error are treated by the use of error correcting code logic without attempting to consider the source of the error. Within the prior art, a variety of techniques have been proposed to correct memory errors either by the use of redundant hardware, by correction of the error itself, or a combination of the two approaches.
Typical is U.S. Pat. No. 3,898,443 which relates to error correction in a memory system utilizing additional logic and control circuitry built with individual IC components. Upon the detection of a memory output error, the incorrect bit is automatically identified and the output from the memory column which provided the error bit is inhibited. A spare memory column is activated and the information, initially in the error column, is transferred to the activated spare column. Consequently, the redundancy taught in the -443 patent is bit column redundancy which relies on the use of parity checking, an address register to hold the failed bit column address, a multiplexer to write the redundant column, decoders to inhibit the failed column and feed-through of the redundant column together with complicated error control circuitry used along with a special test algorithm to identify the failed bit column. This prior art is not directed toward on-chip redundancy and is not applicable to a system where the array chip employs considerable logic functions performed with bit slice outputs.
U.S. Pat. No. 3,860,831 relates to a logic circuit having a redundant element in which an associative memory element is provided to electrically connect a redundant element with a logic circuit. Hence, a failed logic circuit is replaced by a redundant logic circuit using a bistable element to program the path. U.S. Pat. No. 3,665,173 relates to a different technique of stand-by redundancy including three active logic modules and at least one spare module. The system locates the failure of one of the active logic modules and reconfigures the system to bypass the faulty module and substitute a spare therefor. It however, does not relate to arrays of bi-polar devices having implemented systems functioning on-chip to improve overall system performance.
Prior art techniques directed toward using redundancy concepts to detect an error are shown for example in U.S. Pat. No. 3,585,377. This patent discloses the use of a decoder having layers of alternate failure mode logic circuits so that the failure of any individual logic element will always produce an error signal if the failure would cause an output error. IBM Technical Disclosure Bulletin Volume 23, No. 1, Page 213 (June, 1980), discloses a technique which utilizes a decoder circuit for switching off a defective bit and replacing it with a redundant bit provided for that purpose. While theoretically practicable, this approach does not find application to highly functional chips, that is, where a significant number of primary bits are gated onto a small bus before being outputted. The approach cannot be utilized where performance is the primary goal due to the series gating and the load placed on the redundant bit. A different technique of utilizing a separate sense amplifier for redundant word lines and selectively utilizing data read from the redundant word line is disclosed in IBM Technical Disclosure Bulletin, Volume 19, No. 5, Page 1638, (October, 1976). The system requires dual output circuits as well as word decode and compare logic. As such, it does not find application to highly functional chip arrays since it requires a multiplicity of circuits to completely develop the potential in word line redundancy.
An alternative technique for detecting an error by means of creating a redundant function and then comparing for duplicate states utilizing duplicated address decoders is shown in U.S. Pat. No. 4,165,533. A system for achieving on-chip redundancy for an FET chip is shown in IBM Technical Disclosure Bulletin, Volume 14, No. 5, Page 1513 (October, 1971). The system therein employs additional reset lines and decoders for the replacement of a failed word or bit line with a given address by utilizing another word or bit line but still retaining the same address. The setting of the addresses of the bad word lines and/or bad bit lines occurs in latches built on the chip, and therefore requires a latch for each normal decoder and a set of latches for each redundant decoder.
Accordingly, the prior art teaches a variety of techniques for achieving redundancy both on-chip and by ancillary off-chip hardware. A crucial short-coming in the prior art is the failure of any technique for implementing redundancy in the word dimension for a high speed random access memory (RAM) and particularly a memory arrangement where the bit line output stage utilizes on-chip logic making bit redundancy even more difficult to implement. Added on-chip functions are used in advanced bipolar array chips to achieve significant performance gains. Typical is implementation of logic to, for example, select bit slice outputs (a one out of four selection) thereby making conventional bit slice redundancy techniques exceptionally impractical.
It is therefore an object of this invention to define a redundancy scheme for highly functional random access memories.
Another object of this invention is to provide an on-chip redundancy scheme for bipolar memories where the bit-line output stage uses on-chip logic.
Still another object of this invention is to provide a redundancy scheme for high speed random access memories that does not impact on system performance yet improves yield rates by allowing the use of memories having defective components.
A further object of this invention is to provide an on-chip redundancy scheme with minimum component requirements so that chip area criteria are also minimized.